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T
R
I
Q
U
I
N
T
S E M I C O N D U C T O R, I N C .
BLANK B0
A0 B4
A4 B5
A5 B6
A6 B7
A7 (MSB) ECL INPUT BUFFERS MULTIPLEXER
TQ6122
1 Gigasample/sec, 8-bit Digital-to-Analog Converter
Features
SELA V SS (-5 V) DGND
D
Q
BLANKING LOGIC D5 Q5 D6 Q6 D7 Q7 MASTER LATCH
BLANK D0 QBLANK Q0
D4 Q4
CLK CLK
+ - BLANK D0 D4 Q4
BINARY-TO-N-OF-7 SEGMENT ENCODER S1 S2 S3 S4 S5 S6 S7 QS1 QS7 SLAVE LATCH VOUT VOUT + - V REF I BLANK I0 I4 IS1 IS7 50 50 A GND CURRENT-SOURCE ARRAY VSENSE IREF V AA (-5V) BLANK DISABLE VAA
* 1 Gs/s conversion rate * 8-bit resolution * DC differential non-linearity 1/ LSB (0.2%) 2 * DC integral non-linearity 1 LSB (0.4%)
MIXED SIGNAL PRODUCTS
(EXT. CONTROL LOOP) FULL-SCALE ADJUST
QBLANK Q0
BANDGAP REFERENCE
* Settling time 2 ns to 0.4% (est.) * Spurious-free dynamic range (SFDR) 45 dBc typical * ECL-compatible inputs * Synchronous blanking input * 1.3 W power dissipation * 44-pin multilayer ceramic package or unpackaged die
TriQuint's TQ6122 GIGADACTM is a monolithic, 8-bit digital-to-analog converter capable of conversion rates to at least 1000 Megasamples/ second. The TQ6122 DAC may be used for display generation, waveform and signal synthesis, and video signal reconstruction. The TQ6122 features a 2:1 data MUX at the input for ease of interface and offers synchronous blanking capability for maximum ease of use in video applications. It drives complementary 1 V peak-to-peak swings into 50-ohm loads; on-chip 50ohm reverse terminations provide extremely fast settling time. Due to the inherently high speed of TriQuint's one-micron gate Enhancement / Depletion-mode gallium arsenide process, the TQ6122 offers guaranteed operation at clock rates of 1000 MHz, with typical room temperature conversion rates of 1.5 Gs/s without multiplexing and 1.3 Gs/s when using multiplexed inputs. The TQ6122 features output rise and fall times of 500 ps (10% - 90%), symmetric complementary output transitions, and glitch impulse values less than 10 pV/sec. When used for sine wave synthesis, typical spurious and harmonic free dynamic range is 45 dBc. The TQ6122 may be retrofitted into designs which currently use TriQuint's TQ6111, 2, 3, 4M DACs with minimal changes to power supply levels and input and output connections. The part is available in a 44-pin ceramic package or as unpackaged die.
Applications
* Display generation * Waveform and signal synthesis * Video signal reconstruction
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1
TQ6122
Specifications
Table 1. Absolute Maximum Ratings (1,2)
Symbol
AGND, DGND VSS VAA VO, VO (MAX) VI (MAX) II (MAX) PD TC TS
Description
Analog and digital ground Digital power Analog power Analog output (1 V F.S.) Digital input levels Digital input currents Power dissipation Case backside temperature Storage temperature
Min
-2 -7 -10 -2.5 VSS -0.5 -1 -65 -65
Typ
Max
+2
Units
V V V V V mA W C C
+2.5 +0.5 +1 3.0 +135 +150
Notes: 1. Unless otherwise specified: AGND = DGND = 0 V, VSS = VAA = -5 V, VFS = 1 V pk-pk, case temperature = 27 C. 2. Exceeding the absolute maximum ratings may damage the device. The value shown for a particular parameter is determined with all other parameters at their nominal values.
Table 2. DC Characteristics (1)
Symbol
VAA IAA VSS ISS PD VECLREF IECLREF RECLREF CECLREF VIH(DC) VIL(DC) VCLKH (DC), VCLKH (DC) VCLKL (DC), VCLKL (DC) IIN CIN VOUT (MAX), VOUT (MAX) VOUT (MIN), VOUT (MIN)
Description
Analog supply VAA current Digital supply VSS current Power dissipation ECL reference level ECL ref. input bias current ECL ref. input resistance ECL ref. input capacitance Data input HIGH (ECL) Data input LOW (ECL) Clock HIGH input Clock LOW input
Test Conditions
Note 2 VFS = 1 V pk-pk Note 2
Min.
-5.25 50 -5.5 145
Typ.
62 200 1.3 -1.3 0 50 2
Max.
-4.75 80 -4.5 265 1.85 -1.1 +5
Unit
V mA V mA W V mA pF mV mV V V uA pF V V
0.9 Note 3, Figure 1 -1.5 Note 3, Figure 1 VECLREF = 0.2 V -5 Figure 1 DC value (VECLREF = -1.3 V) DC value (VECLREF = -1.3 V) Differential clock, Note 4 Differential clock, Note 4 -1100 VTT VECLREF +0.3 VTT -25
-500 -1500 -0.7 VECLREF -0.3 +25 0.5 +1
Data, clock input bias current VIH = -800 mV, VIL = -1800 mV Data, clock input capacitance In multilayer ceramic package Maximum absolute output level Note 5 Minimum absolute output level Note 5
-1.5
(Continued on next page)
2
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TQ6122
Table 2. DC Characteristics (1) (continued)
Symbol VFS
VZS DVBLANK
Description Full-scale output swing
Zero-scale offset Blanking interval
VBLANK_DISABLE Blank current disable control VREF VSENSE IVREF IREF VIREF ROUT, ROUT COUT VREF input voltage VSENSE output VREF input current Ext. reference current output IREF terminal voltage VOUT, VOUT output resistance Matching of ROUT, ROUT VOUT, VOUT output capacitance Resolution Monotonicity Differential non-linearity Integral non-linearity Full-scale symmetry VFS temperature coefficient
Test Conditions Min Data bits only, 0-0/1-1 input step 0 RL = 50 load VFS = 1 V, no external offset, VBLANK_DISABLE = 0 V Blank input = 1, Notes 6, 7 9 Blank current ON Blank current OFF VFS = 1 V peak-to-peak VAA +0.7 VFS = 0 V peak-to-peak VAA -1 VFS = 1 V peak-to-peak VREF = VAA +0.65 VREF = VAA +1.1 VFS = 1 V peak-to-peak 2 -1.5 44
Typ 1
-35 10.4 -5 (VAA) 0 (AGND) VAA +1.0 VAA +0.8 10 2.5 50 0.2 0.3
Max 1.125
Unit V pk-pk
mV
12
%VFS V V V V V uA mA mA V % pF Bits Bits % F.S. % F.S. mV MIXED SIGNAL PRODUCTS
VAA +1.4 VAA +1.1 1 5 +1 57 2.5 8
8 ( 1/2 LSB) ( 1 LSB) VFS = 1 V peak-to-peak, Note 8 Note 9 0.2 0.4 +4
DNL INL
-4
Notes: 1. Unless otherwise specified: VAA = -5V 5%, VSS = -5 V 10%, VTT = -2V 5%, VFS = 1 V pk-pk, TCASE = 0 to +85 C 2. See the "Power Supplies, Ground and Bypassing" section later in this datasheet for discussion of power supplies. 3. The ECL reference input establishes the switching point for the ECL line receivers used at the DATA, BLANK, and SELECT inputs. (See Figure 1.) IECLREF is the current required to change the internal ECLREF value by about 200 mV. 4. Values shown are for differential clock drive, and apply to both CLOCK and CLOCK inputs. For single-ended drive, the HIGH level should be at least (VECLREF +0.5) volts, but must not exceed -700 mV. The LOW level should be (VECLREF -0.5) volts, but must not go below VTT, where VTT is the ECL termination voltage (nominal VTT = -2 V). 5. VOUT(MAX), VOUT(MAX), VOUT(MIN), VOUT(MIN) represent the limits on the absolute output levels, including offset. 6. Blanking interval is the voltage change (as a percentage of the full-scale output swing) added to VFS when BLANK is asserted. 7. The BLANK DISABLE input turns OFF the blank current (DVBLANK = 0) when held at AGND, and turns it ON when pulled to VAA. 8. Full-scale symmetry is a measure of the balance between VOUT and VOUT. For a full-scale input change (00000000 -> 1111111), the change in VOUT will match the change in VOUT to within 4 mV (1 LSB @ 1 V peak-to-peak). 9. The VFS temperature coefficient is determined primarily by the external reference and loop control op amp.
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3
TQ6122
Table 3. AC Characteristics (1,2)
Symbol
FCLK (MAX) TRCLK,DATA TFCLK,DATA TWH TWL TSETUP THOLD TROUT TFOUT TSETTLE
Description
Maximum clock frequency Clock, data input rise time Clock, data input fall time Duration of clock HIGH Duration of clock LOW Data, control setup time Data, control hold time Output rise time Output fall time Output settling time Glitch impulse
Test Conditions
Unmuxed operation Muxed operation 20% to 80% 20% to 80% Percentage of clock period Percentage of clock period See Figure 7 See Figure 7 10% to 90% 10% to 90% Within 0.4% of final value
Min
1000 1000
Typ
1500 1300 300 300
Max
Unit
MHz MHz ps ps
40 40
50 50
60 60
% % ps ps ps ps ns pV/sec
300 300 2 10
Notes: 1. Unless otherwise specified: VAA = -5V 5%, VSS = -5 V + 10% , VFS = 1 V p-p, TCASE = 0 to +85 C, VECL = -1.3 V, VIH = -0.8 V, VIL = -1.8 V 2. Applies to packaged parts only.
Figure 1. ECL Reference Input Equivalent Circuit
SELA BLANK A7, B7 2 pF ECL INPUT BUFFERS + -
50 I ECLREF EXTERNAL ECL REFERENCE INPUT RECLREF, CECLREF 50 VSS -5 V
50 -1.3V (Nominal, internal)
A0, B0
- +
Figure 2. Definition of VIH, VIL for Data and BLANK Inputs
VIH (MAX) V IH VIH (MIN) V ECL (-1.3 V NOMINAL) VIL (MAX) V IL VIH (MIN)
4
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TQ6122
Figure 3. Typical Digital Input Circuit (Including CLOCK Inputs)
R MICROSTRIP DAC 50 INPUT PROTECTION NETWORK 500 TO INPUT BUFFER 50 V TT -2 V 50 500 VSS -5 V
IN,
C IN
INPUT
Figure 4. VOUT, VOUT, and Input Code Relationships for (A) Typical Instrumentation and (B) Video Configurations
(A) TQ6122 Instrumentation DAC operation (1 V Full-Scale) Blanking current is shunted to ground by tying BLANK DISABLE to AGND and forcing BLANK = 0.
Input Code
Full Scale Full Scale - 1 LSB Half Scale + 1 LSB Half Scale Half Scale -1 LSB Zero Scale + 1 LSB Zero Scale 11111111 11111110 10000001 10000000 01111111 00000001 00000000
VOUT (1)
-0.996 V -0.992 V -0.504 V -0.500 V -0.496 V -0.004 V 0.000 V
VOUT (1)
0.000 V -0.004 V -0.492 V -0.496 V -0.500 V -0.992 V -0.996 V MIXED SIGNAL PRODUCTS
(B) TQ6122 Video DAC Operation (0.679 V Full-Scale) Blanking current is enabled by connecting BLANK DISABLE to VAA.
Input Code
Full Scale Full Scale - 1 LSB Half Scale + 1 LSB Half Scale Half Scale - 1 LSB Zero Scale + 1 LSB Zero Scale BLANK = HIGH 11111111 11111110 10000001 10000000 01111111 00000001 00000000 X.....X
VOUT (1)
-0.679 V -0.676 V -0.343 V -0.341 V -0.338 V -0.003 V 0.000 V -0.750 V
VOUT (1)
-0.071 V -0.074 V -0.407 V -0.409 V -0.412 V -0.747 V -0.750 V 0.000 V
Notes: 1. All values shown for VOUT and VOUT assume identical load resistors (RL1 and RL2 in Figure 5), and no externally imposed output offset voltage (VOS in Figure 5). Zero-scale offset is ignored.
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5
TQ6122
Figure 5. Output Equivalent Circuit, Showing Terminated 50-ohm Transmission Line Loads
R OUT, C OUT IOUT
Z 0 = 50 NON-INVERTING OUTPUT (VOUT ) 1000 pF 50 R T1 50 RL1 100 pF 50 R T2 50 RL2 0.1uF V OS (SEE FIG. 18)
(-3V TO +4V)
DIGITAL INPUT AGND
(FOR NO OUTPUT OFFSET)
INVERTING OUTPUT (VOUT ) I OUT BOUNDARY OF DAC Z 0 = 50 "FAR-END" TERMINATIONS
Figure 6. Definition of TWH and TWL
T WL(CLK)
50%
T WH(CLK)
6
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TQ6122
Figure 7. TQ6122 Data and Control Timing
CLOCK TDS TDH DATA TSS TSH SELA
Symbol
TDS TDH TSS TSH
Description
Data setup time Data hold time (2) SELA setup time (1,3) SELA hold time (2,3)
(1)
Typical @ 25 C
0 +325 +350 -100
Unit
ps ps ps ps
Notes: 1. Setup time is defined to be positive for data or control transitions occurring before the negative-going edge of the clock. 2. Hold time is defined to be positive for data or control transitions occurring after the negative-going edge of the clock. 3. While SELA does not strictly have a setup and hold time, it is convenient to express its allowed transition region limits in these terms.
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7
MIXED SIGNAL PRODUCTS
TQ6122
Mechanical Characteristics
The TQ6122 DAC is packaged in a proprietary 44-pin multilayer ceramic package which provides high-speed, controlled-impedance interconnects and integral power supply bypassing. The leads are set on 0.050" centers, and are formed for gull-wing surface mounting. Figure 8 shows the pinout diagram of the packaged IC as seen from the top, opposite the cavity side; Figure 9 lists pin numbers, names and I/O levels. Figure 10 illustrates the pertinent dimensions of the package and Figure 11 shows the mounting footprint. Since the TQ6122 dissipates on the order of 1.3 W, adequate heat sinking is essential for proper operation of the device. Figure 12 shows one possible heat sink arrangement based on a multi-finned "Top Hat" heat sink available from Thermalloy. An environment with a minimum of 100 fpm (feet per minute) of forced air cooling is assumed; >200 fpm is preferred.
Figure 8. TQ6122 Pinout
VSENSE BLANK DISABLE AGND VOUT VOUT AGND AGND AGND VSS
12 11
VAA VREF
VAA IREF ECL REF A0 A1 DGND A2 A3 A4 A5 VSS
23
TQ6122AM
TOP VIEW OF MLC-44 PACKAGE AS IT SITS ON CIRCUIT BOARD (CAVITY IS DOWN)
PIN 1
34
VSS CLOCK CLOCK N/C SELA DGND BLANK B7 B6 B5 VSS
VSS A6
Notes: 1. A7, B7 = MSB inputs 2. N/C = no internal connection
Figure 9. TQ6122 Pin Descriptions
Pin
1, 11, 12,
33, 34, 44 2 3 4 5 6, 28, 37, 40 7 8 9 10 13-15, 18 16 17 19 20 B5 B6 B7 (MSB) BLANK DGND SELA -- CLOCK CLOCK AGND VOUT VOUT BLANK DISABLE VSENSE 600 mV pk-pk centered at -1.3 V @ DC 600 mV pk-pk centered at -1.3 V @ DC 600 mV pk-pk centered at -1.3 V @ DC 600 mV pk-pk centered at -1.3 V @ DC 0V 600 mV pk-pk centered at -1.3 V @ DC No connection 1V pk-pk centered at -1.3 V @ AC 1V pk-pk centered at -1.3 V @ AC 0V 0 V to -1 V -1 V to 0 V Enable = VAA (IBLANK = ON) Disable = AGND (IBLANK = OFF) VAA + 0.8, for VFS = 1 V pk-pk
Signal
VSS
Interface Level (Typ.)
-5 V
Pin
21 22, 23 24 25 26 27 29 30 31 32 35 36 38 39 41 42 43
Signal
VREF VAA IREF ECL REF A0 (LSB) A1 A2 A3 A4 A5 A6 A7 (MSB) B0 (LSB) B1 B2 B3 B4
8
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A7 DGND B0 B1 DGND B2 B3 B4 VSS
Interface Level (Typ.)
VAA +1, for VFS = 1V pk-pk -5 V 2.5 mA for VFS = 1V pk-pk -1.3 V 600 mV pk-pk centered at -1.3 V @ DC 600 mV pk-pk centered at -1.3 V @ DC 600 mV pk-pk centered at -1.3 V @ DC 600 mV pk-pk centered at -1.3 V @ DC 600 mV pk-pk centered at -1.3 V @ DC 600 mV pk-pk centered at -1.3 V @ DC 600 mV pk-pk centered at -1.3 V @ DC 600 mV pk-pk centered at -1.3 V @ DC 600 mV pk-pk centered at -1.3 V @ DC 600 mV pk-pk centered at -1.3 V @ DC 600 mV pk-pk centered at -1.3 V @ DC 600 mV pk-pk centered at -1.3 V @ DC 600 mV pk-pk centered at -1.3 V @ DC
TQ6122
Figure 10. Package Dimensions
0.015 0.050 0.125 0.035
PIN 12
TOP VIEW
0.65 SQUARE
0.805 NOMINAL
PIN 1 0.060 All Dimensions in Inches 0.005
Figure 11. Mounting Footprint
PIN 12 PIN 23
0.025 0.050
0.425 0.350
Package Outline (For Reference Only) SOLDER PAD PIN 34 PIN 1 All Dimensions in Inches
Figure 12. Heat-Sink Mounting Arrangement (heat sink not included)
THERMALLOY TYPE 2291C TOP
Use Loctite "Output" Thermal Conductive Adhesive (Loctite item number 00241) or equivalent to attach heat sink base to IC.
THERMALLOY TYPE 2291C BASE DAC IC
THERMAL ADHESIVE
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9
MIXED SIGNAL PRODUCTS
TQ6122
Circuit Description
The TQ6122 DAC is based on a current-steering architecture in which weighted currents are switched by an array of differential-pair switches into either the VOUT or VOUT output, depending on the state of the input data and blanking bits. Essentially, the DAC is comprised of six circuit blocks: the input buffer, the data multiplexer, blanking logic, master/slave latch array with segment encode logic, differential-pair switches, and the current source array. (See figure on page 1.) Input Buffers The input buffers compare the ECL data and control input signals with the ECLREF level, amplify the difference, and translate this signal to the logic levels used within the IC. By default, the ECL reference is set by an internal generator; however, for best performance and maximum noise margin over temperature, power supply, and device-to-device variations, the user should provide an external level. For general-purpose applications, a simple resistive divider between DGND and VTT will suffice. For extreme environments or for maximum performance, the ECLREF level should be slaved to the centerpoint of the incoming data. Refer to the "Digital Inputs and Terminations" discussion later in this document for additional information. Note that the data inputs are complemented to indicate that an increasing input value results in the VOUT level moving more negative. Data Multiplexer The DAC makes provision for accepting data from either of two sources: from a single 8-bit-wide word at the full conversion rate, or from two 8-bit-wide halfspeed words which are multiplexed together inside the DAC under the control of the SELA input. In use, the SELA input is set HIGH to select the A-Word data and
LOW to select the B-Word. It is generally best to use the A-Word input when operating the DAC unmultiplexed, although the B-Word supports full-rate transfers. Blanking Logic A separate BLANK input is included to allow the DAC to be used in video display applications. When asserted LOW, the BLANK input has no effect on the operation of the DAC, and the state of the input data words controls the positions of the current switches. When BLANK is asserted HIGH, however, all internal data bits and the internal blanking bit are synchronously forced HIGH at the next negative-going clock transition, causing the VOUT output to go to its most negative level. This level is the sum of the normal level associated with an input code of 11111111 plus the increment due to the blanking current being steered away from the VOUT output to VOUT. See Figure 4 (B). In order to provide more latitude in the timing of the BLANK signal, the BLANK input is sampled only when the A-Word is selected. When the B-Word is selected, the state of the BLANK input at the time the SELA control line goes LOW is held stable until SELA again goes HIGH. In situations where blanking is not used, it is important that the BLANK input be tied to a solid logic LOW to prevent accidental assertion of BLANK = HIGH. Note also that when the DAC is used in the unmultiplexed mode, the data should be brought in on the A-Word inputs, since with SELA = LOW (as would be the case for B-Word operation), a transient HIGH level at the BLANK input would never be cleared and the DAC would lock up. The BLANK_DISABLE pin is normally tied to the VAA rail, allowing IBLANK to flow to the differential-pair switch and then to the selected output. For applications which do not use blanking, however, the standing offset in the VOUT output due to the unswitched
10
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TQ6122
blanking current would be undesirable. For cases such as these, the blanking current may be completely turned off by connecting the BLANK_DISABLE pin to AGND. Master/Slave Latch With Encode Logic A nine-wide master latch registers the data coming from the multiplexer and blanking logic. The latch outputs are then split into two groups. The top three bits are translated into a seven-level thermometer code by a binaryto-N-of-seven encoder, while the lower five data bits and the blanking bit are simply delayed. The seven encoder outputs and the six delayed data and blanking bits are re-registered in a slave latch to minimize skew, which, in turn, reduces the glitch impulse. Latch timing is set up such that the slave latch is in the "sample" mode when the input clock is LOW, meaning that the analog output is updated at the falling edge of the clock. Current Switches The thermometer code outputs of the slave latch array drive seven switches, each of which steers a current equal to 1/8 of the full-scale step amplitude. The five encoded data bits, on the other hand, switch currents
with effective binary weightings from 1/16 of full scale down to 1/128 of full scale. The blanking bit steers a current which is nominally 10.4% of the full-scale amplitude. Current-Source Array The current-source array is the heart of the DAC from an analog standpoint, and is responsible for generating the segment, bit, and blanking currents. The maximum full-scale current IFS (less IBLANK) is about 45 mA, providing a 1.125 volt maximum swing into the 50ohm external load. The blanking current is nominally 10.4% of IFS, corresponding to a 10-unit IRE blanking interval of 71 mV when the full-scale output is set to 0.679 volt. The IREF current tracks IFS, with a nominal value of 2.5 mA for IFS = 40 mA (i.e., 6.25% of IFS). Figure 13 (A) illustrates the basic circuit of the currentsource array, which consists of a set of current sources ranging from the 5 mA segment currents to the binaryweighted current sources for the lower-order bits. The circuit design utilizes source degeneration, averaging, and linear gradient cancellation techniques to obtain matching consistent with up to 10-bit linearity.
MIXED SIGNAL PRODUCTS
Figure 13 (A). Current-Source Array Circuit -- VSENSE -Based Control Method
VOUT VOUT DIFF-PAIR SWITCH (TYPICAL, 15 PLACES)
BLANK IREF 2.5 mA (NOM) CASCODES I BLANK
BLANK
I SEG 1
I SEG 7
I B4
I B3
I B0 V BIAS (INTERNAL)
+ - EXT REF. 0.8 V NOM, FOR 1 V F.S. OUT
VREF
2W
3.56W
4W
4W
2W
W
VSENSE RS
RS 1.77
RS 2
RS 2 VAA - 5V
RS
2RS
RLSB
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11
TQ6122
The absolute value of the current-source array output is determined using an off-chip (silicon) reference generator and op amp in a feedback-loop arrangement. In Figure 13 (A), the drop across the source degeneration resistors is compared with the level set by the external reference. Under conditions of 1 V peak-to-peak full-scale output swing, the voltage between the VSENSE and VAA pins of the DAC will be in the range of 0.8 V to 1.1 V, with VREF being in the range of 0.7 V to 1.4 V (i.e., VREF may lie above or below VSENSE by several hundred millivolts). Note that, for this control method, the IREF terminal must be connected to ground. An alternative means of controlling the current-source array output is shown in Figure 13(B), with the advantage that now the reference current is being sensed after flowing through a path identical to that of the bit and segment currents. Thus, any error which may have occurred due to leakage will be directly corrected. Here, the VSENSE pin is left disconnected and the IREF current flows to ground through a stable
resistor. The value of the resistor should be chosen to drop about 1 volt under the desired operating conditions, but under no circumstances should the voltage at the IREF pin be allowed to drop below -1.5 V, or the linear relationship between IREF and IFS will be degraded. The primary limitation on the maximum output current is the adjustment range of VSENSE: if the value of {VSENSE - VAA} exceeds about 1.2 V, the bottom currentsource FETs begin to lose "headroom" by running up against the sources of the cascode transistors, causing the total current to begin limiting, as well as degrading, the linearity. If the designer is willing to accept somewhat degraded linearity and/or slightly higher power dissipation, VAA may be taken down to -6 volts or so, allowing VREF to be adjusted to give {VSENSE - VAA} a maximum value of about 1.5 V. This translates to an output current of about 50 mA or 1.25 V peak-topeak into the load. Note that under these conditions, the device will not sustain any damage, but full-spec operation of the DAC is not guaranteed.
Figure 13 (B). Current-Source Array Circuit -- IREF -Based Control Method
VOUT VOUT
BLANK IREF 2.5 mA (NOM) I BLANK
BLANK
EXT REF. < 1.5 V
V BIAS (INTERNAL) VREF
+ -
VSENSE (N/C)
VAA - 5V
12
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TQ6122
Application Information
Figure 14 illustrates the basic connection of the DAC, showing details for power supplies, data and clock inputs, and outputs terminated in 50-ohm transmission line loads. Some issues relating to circuit board layout are also addressed.
Figure 14. Basic DAC Setup
A5 u = Microstrip or other transmission line A4 1000 pF VTT PLANE 50 1F VSS PLANE .01F A6 A7 B0 B1 B2 B3 B4 u u DGND u u DGND
NOTE 5 NOTE 5
u
u
A1 A2 A0 .01F uu uu A3
EXT. ECL REF.
Split power supply planes here to minimize noise coupling into analog circuitry. Use a common plane for analog and digital grounds. VAA PLANE 1uF .01F 1000 pF 2.5 K 2.5 K MC33071 VCC + - VAA 620 MC1403A + - VAA
VOUT (VAA + 2.5 V) 1K 1K Adjust for desired full-scale output V AA (VAA +1 V)
.01F
1000 pF
50
VSS
DGND
IREF VAA ECL VREF REF. VSENSE BLK.DIS. AGND VOUT VOUT AGND AGND DGND VSS
VEE
(IBLANK = OFF) ZO = 50 VOUT VOUT
1000 pF u u u VTT PLANE
Short microstrip or buried stripline
VSS VSS
DGND DGND
VSS PLANE 1F .01F 1000 pF 1000 pF .01F 50 L1
-5 V SUPPLY
VSS PLANE 1uF A7, B7 = MSB VSS = -5 +0.5 V VAA = -5 +0.25 V VTT = -2 V
VTT PLANE VSS PLANE VAA PLANE u u u u u u u .01F 1000 pF SELA CLK CLK
L2
L1 , L2 = Fair-Rite 2743001111
B5 B6 B7 NOTE 5 BLANK NOTE 5
Notes: 1. All resistors to VTT are 50-ohm, 1/8 Watt, surface-mount, mounted as close to the IC as possible. 2. All VSS and VTT capacitors are rated 15 V. All VAA capacitors are rated 25 V. 3. Use either surface-mount components or keep minimum-length leads on all resistors and capacitors. 4. For best noise isolation, the analog supply (VAA) and digital supply (VSS) should connect at only one point, via decoupling networks such as ferrite beads. 5. The input circuitry for B0-B7, BLANK, and SELA are the same as for A0-A7. 6. For questions regarding board layout, please contact the factory.
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13
MIXED SIGNAL PRODUCTS
VAA
(I BLANK = ON)
TQ6122
Power Supplies, Ground and Bypassing To minimize noise coupling, the digital and analog power supplies should be returned to a single-point ground, and power supply buses to the IC should have minimum impedance (power planes are best). The supplies themselves should be well bypassed at high and low frequencies, which requires the use of several different parallel capacitors as shown. The values are not particularly critical; however, due to the fact that a capacitor looks inductive above its self-resonant frequency, one needs to use several different values in parallel, ranging from microfarads to nanofarads, in order to provide adequate wideband bypassing. For best results, use leadless ceramic chip capacitors for bypassing, although leaded components will work satisfactorily if higher noise can be tolerated. A common ground plane has been found to give the best performance. For best results and minimum noise, the digital and analog supplies should be physically separated on the circuit board. When using a common -5 V feed, the VSS and VAA planes should be isolated by ferrite beads (Fair-Rite P/N 2743001111 or equivalent) as shown in Figure 14. Using separate LM337MT regulators downstream of the ferrite beads will provide better isolation.
Digital Inputs and Terminations The TQ6122 DAC is designed to accept ECL logic levels at all data and control inputs. All ECL inputs, with the exception of the clock (see below), are single-ended and are compared to the ECL threshold reference of -1.3 Volts (nominal) in the input buffers of the DAC. The ECL reference input equivalent circuit is shown in Figure 1. Several options are available to the user for externally setting the ECL reference level. The simplest option is that of a voltage divider between DGND and VTT, setting the ECL termination voltage as shown in Figure 15 (A). The nominal value for ECLREF is -1.3 V; however, due to input offset variations among the input buffers or variations in VTT, some adjustment above or below -1.3 V may give the best results. A good way to settle ECLREF is to slave the ECL reference level to the center (switching) point of the input data signal. This may be accomplished in two ways: either use the VBB generator output of the device which is generating the ECL signals supplied to the DAC, or use an inverter with input and output connected together to generate a level equal to the switching threshold. See Figure 15 (B). Note that the ECLREF generator should be able to source and sink up to approximately 5 mA, since the input resistance is about 50 ohms, against an internal -1.3 V (nominal) voltage source. An additional op amp may be used to give more flexibility or more robust drive. See Figure 15 (C).
Figure 15. External ECL Reference Generator (A) (B)
(C)
200 ECL Reference input or unused clock (CLK) input
EXTERNAL ECL INVERTER
ECLREF DAC INPUT
50 V TT -2 V
50 V TT -2 V
(OPTIONAL OP AMP)
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- +
TQ6122
Clock Input In order to realize the full speed potential of the DAC, a clock with an input swing of at least 1 V peak-to-peak, nominally centered on -1.3 V, is required. The clock may be applied in either single-ended or differential fashion. Because a differential clock provides maximum speed and best control of the relationship between clock and output transitions, as well as minimum noise, it is the preferred solution. For single-ended clock drive, the customer must drive the unused CLOCK input with an external ECL reference level, which may be generated using a resistive divider or, for best results, an external inverter tied back on itself. See Figure 15. Input Line Termination As shown in Figure 14, data, control, and clock inputs should be terminated in 50 ohms to VTT, consistent with good ECL practice. For best results, keep terminations physically small -- surface-mount "chip" resistors work very well -- and locate them as close to the IC as possible. The VTT bus should also be locally bypassed to digital ground, using chip capacitors placed close to the terminations. The DAC offers good performance for -2.5 V < VTT < -2 V, where the use of VTT < -2 V may allow the designer to eke out the last bit of performance in a noisy or marginal drive-level environment. Current-Source Control Loop As illustrated previously in Figure 13, and shown in detail in Figure 16, the bit current sources are controlled by placing them in a feedback loop which compares the drop across a current-sensing resistor with a stable reference. For nominal 1 Volt full-scale output swing, the VREF-to-VAA voltage will be in the 0.8 to 1 V range, and may be derived from a zener or, better still, a bandgap reference such as the 2.5 V Motorola MC1403A. The output of the bandgap
reference will have to be divided down before being applied to the control op amp, and some means should be provided to trim the output to compensate for VOUT load resistor variations. The op amp must have input common-mode and output drive ranges which extend down to within at least 0.5 Volt of the negative rail for maximum control range. For best noise immunity, both the reference generator and the op amp should share a point connection to the VAA rail, close to the DAC. The Motorola MC33071 op amp is suitable for this application. Standard linear design techniques should be used to minimize thermal drift and offset. Note that the temperature coefficient of the nichrome resistors used in the DAC is on the order of +6 ppm/C. Figure 16 shows a typical reference control loop circuit.
Fig. 16. Typical External Current-Source Control Loop
VAA PLANE 1uF 0.01 1000 VCC IREF VAA VREF VSENSE BLK.DIS. AGND VOUT VOUT AGND AGND DGND
V AA
MC1403A + - VAA
VOUT (VAA + 2.5 V) MC33071 + - VAA 620 (I BLANK = ON) (I BLANK = OFF) V OUT V OUT 1K 1K V AA (V AA +1 V)
2.5 K 2.5 K
VEE
Figure 17 illustrates the relationship between control input VREF and the full-scale output swing. Note that the full-scale swing may be reduced below 0.25 V peak-topeak by pulling VREF below VAA. However, this necessitates a separate negative supply for the control
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MIXED SIGNAL PRODUCTS
TQ6122
op amp and reference generator, which may decrease the VAA supply rejection. In circuits which use different negative rails for the DAC VAA supply and the op amp, VREF should be clamped to no more than two diode drops below VAA, and a current-limiting resistor should be included at either the op amp output or between its negative supply input and supply input. In the event of turn-on transients and large excursions in the op amp supply before VAA has settled out, these precautions will help prevent breakdown of circuitry within the DAC.
Blanking Current Programming The blanking current (IBLANK in Figure 13) is turned off by connecting the BLANK_DISABLE pin to AGND to divert the current away from the blank switch and the output of the DAC, and turned on by connecting BLANK_DISABLE to VAA. Output Equivalent Circuit Figure 5 illustrates the equivalent circuit of the two DAC outputs. Each of the bit current sources is switched into either the VOUT or the VOUT output, depending on the data stored in the slave latches. A pair of internal 50-ohm resistors are connected from VOUT and VOUT to analog ground (AGND), and provide reverse termination for the analog output transmission lines. Although in principle there is no restriction on the load impedance applied at the outputs, in practice, the best performance will be obtained when driving a 50-ohm terminated transmission line. This is very important from a settling standpoint, since reflections from non50-ohm loads will superimpose with new transitions and interfere with settling. The general rule for terminating the outputs is "the cleaner, the better." Output Zero-Scale Adjust
Figure 17. Typical VREF-to-VAA Transfer Characteristics
1.25 1.125 1.00 (Maximum recommended)
VOUT
(Volts p-p)
0.50
0.75
0.25
-1.0
0
0.5
1.0
1.25
V REF to VAA
(Volts)
Full-Scale Output Adjust The procedure for setting the full-scale output range is quite straightforward, and involves monitoring the output level(s) using a DVM. With the DAC connected to its actual VOUT and VOUT load(s), the output is alternately switched between steady state zero- and full-scale levels, and the reference is adjusted until the desired full-scale transition amplitude is obtained. The clock must be running and the BLANK input set to "0". Alternatively, for a DDS application, a spectrum analyzer or a power meter may be used to monitor the full-scale output power.
The output baseline, or "zero-scale" level, may be adjusted by returning the far-end termination resistors to a well-bypassed supply level other than ground. For this general situation, reference Figure 5, the instantaneous output voltages VOUT and VOUT are given by:
VOUT = VOS ( VOUT = VOS (
RT1
RL1 + RT1
) - | IOUT | (RL1 || RT1)
RT2 ) - | IOUT | (RL2 || RT2) RL2 + RT2
IOUT = IOUT =
( Digital Input ) IFS
255 Digital Input 255
(1 -
) IFS
IFS = Summation of all individual bit currents Digital Input = Decimal equivalent of the binary input word
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TQ6122
For the case of RL1 = RL2 = RT1 = RT2 = 50 ohms, VOS is attenuated by 50%. An overriding factor in setting the output offset is the requirement that VOUT and VOUT always remain within the device's output compliance range of -1.5 V to +1 V. Note also that in the case of the video application of the DAC, the value of the blanking current IBLANK and the state of the BLANK input must be included in the expressions for VOUT and VOUT. An alternative method of offsetting the output involves injecting an offset current at the output. This may be done using a current source in the form of either a resistor or a transistor as shown in Figure 18(A). The resistor has the advantage of minimizing perturbation of the transmission line impedance, with the
disadvantage of requiring a large supply voltage. In general, a 1/8 to 1/4 W carbon-composition resistor with a value of 500 to 1000 ohms will give good performance. Keep the lead lengths short when attaching to the circuit board and bypass the driven terminal of the resistors with a 1000 pF to 0.01 F SMT (surfacemount) capacitor network to the ground plane. A transistor current source, on the other hand, requires much less power supply overhead, but adds more capacitance to the transmission line. If a transistor is used, it should be a high-FT device with low CCB or CDG ( 0.5 pF, if possible) and installed with short leads. Capacitive coupling provides a means of obtaining an output centered on 0 volts. However, simply adding a coupling capacitor at one (or both) of the outputs will cause the DC output level to exceed the -1.5 V output compliance limit. The way to circumvent this problem is to add an offset current between the DAC output and the coupling capacitor (as discussed above), or to add a low-loss 50-ohm pad between the DAC and the capacitor, as shown in Figure 18(B). A "T" or "" attenuator topology is acceptable, having 1 dB to 3 dB of attenuation. The characteristic impedance must be consistent with the overall system impedance, typically 50 ohms. This approach works, although the lower limit on the output level tends to be very close to the -1.5 V compliance limit for 1 V full-scale output swings, so some care and verification will be required.
Figure 18(A). Alternate Output Offset Current Generators
VOS 1000 pF R1 0.01 uF 500 - 1 K Short Lead 1/8 - 1/4W Carbon Comp. R3 R2 High-F T Low C JE Device Short Lead RE VT
50 Ohm
50 Ohm
Figure 18(B). AC Coupling of Outputs
0 VOLT VMIN MIMIMUM-LOSS PAD (1-3 dB) 0 VOLT
DAC
50
Note: VMIN must not exceed the lower output compliance limit of -1.5 V for proper operation. If VMIN < -1.5 V, decrease the DAC output swing by adjusting the VREF drive to the control op amp.
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MIXED SIGNAL PRODUCTS
TQ6122
Typical AC Performance
Figures 19 through 23 show typical AC performance of the TQ6122. Figures 19A and 19B illustrate the response of the DAC to an unmultiplexed counter input at 1 Gs/s and 1.5 Gs/s, respectively. Blanking is enabled in both cases. The small glitches appearing at 1/8 of full-scale intervals are shown in more detail in Figure 22.
Figure 19 (A). Unmuxed Ramp at 1000 Ms/s with Blanking (Guaranteed, 0 to +85 C)
Figure 19(B). Unmuxed Ramp at 1500 Ms/s with Blanking (Typical, +25 C)
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TQ6122
Figure 20(A). Muxed Ramp at 1000 Ms/s with Blanking
Multiplexed behavior is shown in Figure 20A and 20B, with a counter input muxed against fixed levels at 1000 Ms/s and at 1350 Ms/s, respectively. In Figure 20A, the ramp is muxed against a steady state mid-scale value, while in Figure 20B, the steady state input is 11111111. The apparent droop in the top level in Figure 20B is an artifact of the sampler. Figures 19A, 19B, and 20A show the effects of blanking, while in Figure 20B, the BLANK input is held LOW, demonstrating the repetitive nature of the waveform.
Figure 20(B). Muxed Ramp at 1350 Ms/s with Blanking Disabled
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MIXED SIGNAL PRODUCTS
Note: In Figure 20(A), A0-A7 are switched, B0-B6 are LOW, B7is HIGH and BLANK is switched. In Figure 20(B), A0-A7 are switched, B0-B7 are HIGH, and BLANK is LOW.
TQ6122
Figure 21. Typical Full-Scale Transitions at VOUT and VOUT (fCLK = 1000 MHz)
Figure 21 illustrates the symmetry of complementary full-scale transitions at VOUT and VOUT, while Figure 22 depicts a typical worst-case glitch of 6 pV/sec.
Figure 22. Typical Worst-Case Glitch Impulse (fCLK = 1000 MHz)
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TQ6122
Figure 23(A). Synthesized Sine Wave Output
Figure 23(A) shows a 1 Gs/s, 58.6 MHz sine wave, and Figure 23B shows its corresponding spectrum. The spurious-free dynamic range is 46 dBc, a typical value for the device. In Figure 23(B), the DAC output is attenuated by 6 dB going into a spectrum analyzer.
Figure 23(B). Spectrum of a 58.5 MHz Sine Wave at 1 Gs/s
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MIXED SIGNAL PRODUCTS
TQ6122
Figure 24. Complex Modulated Sine Wave Pattern at 1000 Mb/s
Figure 24 shows a modulated sine wave as an example of a more complex waveform.
Figure 25. Chip Dimensions, Topography, and Padout
A0 (LSB) ECL REF DGND DGND IREF DGND VAA VAA VSS A1 A2 A5 VSS A3 A4
VAA VAA VREF VSENSE BLANK DISABLE AGND AGND AGND VOUT VOUT AGND VOUT VOUT AGND AGND
VSS VSS A6 A7 (MSB) DGND DGND B0 (LSB) B1 DGND DGND B2 B3 B4
Notes:
1. Dimensional limits unless otherwise specified: +2 mils (+51 M). 2. Pins labeled N/C are not connected internally.
VSS VSS VSS
B7 (MSB)
VSS
VSS
BLANK
DGND
DGND
DGND
CLOCK
SELA
DIE SIZE: 129 Mils x 111 Mils (3110 M x 2660 M)
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CLOCK
VSS
VSS
N/C
B6
B5
TQ6122
Figure 26. Package Labelling (44-pin packaged version) See Figures 10, 11 and 12 for package dimensions and heat-sink mounting information.
BEVELED CORNER
1 TQS USA TQ6122-M YYWW XXXX
YYWW - Date Code XXXX - Lot Number
Component
Lead Lead Plating
Material
Kovar Lead/tin alloy
Ordering Information
TQ6122-M TQ6122-D ETF6122
Additional Information
8-bit, 1 Gs/s DAC in 44-pin package 8-bit, 1 Gs/s DAC, die only Engineering Test Fixture with 6122 device
For latest specifications, additional product information, worldwide sales and distribution locations, and information about TriQuint: Web: www.triquint.com Email: sales@tqs.com Tel: (503) 615-9000 Fax: (503) 615-8900
For technical questions and additional information on specific applications: Email: applications@tqs.com
The information provided herein is believed to be reliable; TriQuint assumes no liability for inaccuracies or omissions. TriQuint assumes no responsibility for the use of this information, and all such information shall be entirely at the user's own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. TriQuint does not authorize or warrant any TriQuint product for use in life-support devices and/or systems. Copyright (c) 1997 TriQuint Semiconductor, Inc. All rights reserved. Revision 1.0.A October 1997
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MIXED SIGNAL PRODUCTS

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